The present invention relates to a semiconductor device and a tape automated bonding (hereinafter, referred to as TAB) tape used in the semiconductor device and, more particularly, to a semiconductor device of a chip scale package (hereinafter, referred to as CSP) structure and a structure of a TAB tape used in the semiconductor device.
In packaging of a semiconductor device, a semiconductor device of a conventional lead on chip structure is widely employed as a basic structure of a 16M DRAM and so on because of high density mounting capability and high design freedom of a semiconductor chip and a semiconductor device. However, a bonding pad of a semiconductor chip such as a large scale integrated semiconductor circuit and an inner lead of a semiconductor device lead frame are connected with a bonding wire such as a gold wire or the like. According to this connecting method, that is, the ball bonding method by heat pressing using the bonding wire such as the gold wire or the like, it is difficult to reduce the pitch between the bonding pads below 100 xcexcm and accordingly to limit the wiring design because of limitations in the size of a heating tool which forms a ball in a top end of the bonding wire by heating and in the size of a tool such as a capillary which holds and moves the bonding wire and press-bonds the ball formed in the top end of the bonding wire to the bonding pad of the semiconductor chip.
Further, the connecting method between the bonding pad of the semiconductor chip such as a large scale integrated circuit or the like and the lead of the TAB tape in the conventional TAB is performed by forming a vamp made of gold or the like in the bonding pad of the semiconductor chip, and tinning the corresponding metal lead to be connected through a gold-tin alloy bonding method (refer to xe2x80x9cVLSI packaging technology (the first volume)xe2x80x9d, pp74-97, published by Nikkei PB Company). According to this method, it is possible to set the pitch between the bonding pads to 50 to 100 xcexcm. However, since the vamps need to be formed in the pre-process of semiconductor pitch (micro-machining of the wafer), there are problems in addition of processes and in price of the semiconductor device. Therefore, the method is not suitable for being applied to a package containing a semiconductor chip like a large scale integrated circuit of small batch production such as an ASIC device.
A method of face down connecting a semiconductor chip such as a large scale integrated circuit onto a ceramic board or the like by providing solder vamps on a bonding pad of the semiconductor chip is applied to a mass production process as a high integrated mounting technology in a super-computer field (refer to xe2x80x9c""97 Symposium on New Technology of VLSI packagingxe2x80x9d, p126, held on Mar. 3-4, 1997, sponsored by the Society for Semiconductor Packaging Technology Study). This method has problems in that the solder bonding vamps need to be formed on the surface facing the semiconductor chip because the vamp pitch, that is, the bonding pitch is as wide as approximately 250 xcexcm, and in that the cost becomes high because an alumina ceramic material having a linear thermal expansion coefficient near the linear thermal expansion coefficient of the silicon substrate forming the large scale integrated circuit must be used in order to moderate thermal stress acting on the bonding portions. The reason why the vamp pitch in this method is as wide as approximately 250 xcexcm is that making of wiring formed on the ceramic substrate to be finer is more difficult than in the case of the TAB.
The semiconductor device 1xe2x80x2 of a CSP structure called as xcexcBGA (BGA: Ball Grid Array) structure as shown in FIG. 11, developed by TESSERA Inc., has a structure in which solder balls 3xe2x80x2 as externally connected members are arranged in a region inside the periphery of a semiconductor chip 2xe2x80x2. According to this structure, as the size of the semiconductor chip 2xe2x80x2 is decreased with progress of the micro-machining technology of the wafer, the pitch between the solder balls 3xe2x80x2 as externally connected members needs to be reduced as shown in FIG. 13, as well as the pitch between bonding pads 4xe2x80x2 of the semiconductor chip 2xe2x80x2. However, there is a disadvantage in that when the pitch P between the solder balls 3xe2x80x2 is decreased, compatibility among packages cannot be maintained and wiring design of a print board needs to be changed.
Since the xcexcBGA is widely used as a structure of a semiconductor device for a potable apparatus such as a flash memory or the like, it is strongly required to reduce size and cost of the semiconductor chip. The most widely employed method of reducing cost of a semiconductor chip is a chip shrink technique in which the size of the semiconductor chip is decreased using the wafer micro-machining technology to increase the number of chips obtained from one single wafer. FIG. 13A shows a feature before the chip shrinking, and FIG. 13B shows a feature after the chip shrinking. Further, the xcexcBGA structure developed by TESSERA Inc. has a disadvantage in that it is difficult to employ the chip shrink technique in connection with the xcexcBGA structure because there is the above-mentioned problem when the size of the semiconductor chip is decreased.
Furthermore, in the above-mentioned xcexcBGA structure, the TAB tape 5xe2x80x2 used for the member to construct the package is formed by making holes in an insulator tape 6xe2x80x2 member made of polyimide or the like through press-working. Therefore, there is a limitation in machining of the micro-holes because it is difficult to make the micro-holes having a diameter as small as the size of the bonding pad, and there is a problem in that when a TAB tape of a three-layer structure having a bond between a metallic film and the insulator tape is used, the press-working of the inside surface of the holes squeezes out the bond from bonded edge portions.
In addition to the above, in the above-mentioned xcexcBGA structure, an elastomer 8xe2x80x2 having a length of approximately 100 xcexcm is arranged between the semiconductor chip 2xe2x80x2 and the TAB tape 5xe2x80x2 as a thermal stress modulating member. However, according to this structure, in order to connect a metallic film lead 7xe2x80x2 of the TAB tape to the bonding pad 4xe2x80x2 of the semiconductor chip 2xe2x80x2, the lead 7xe2x80x2 needs to be formed so as to have an S-shaped bent portion depending on a level difference to the bonding pad 4xe2x80x2. In order to do so, a tool having a cross-shaped groove in the top end is used as the bonding tool for forming the lead in the S-shape to connect it. The lead 7xe2x80x2 is bent toward the bonding pad 4xe2x80x2 of the semiconductor chip 2xe2x80x2 while the lead 7xe2x80x2 is being held by the groove of the tool, and connected to the bonding pad by controlling so that the lead 7xe2x80x2 is slightly moved in the horizontal direction to a desired position.
Therefore, from the problems caused from the structure and the operation of the bonding tool, it is difficult to bend and move the lead 7xe2x80x2, to be wired in a slanting direction, in the horizontal direction toward the bonding pad 4xe2x80x2 and to connect to the bonding pad, in a case where the bonding pads 4xe2x80x2 are arranged in the corners of the semiconductor chip 2xe2x80x2, as shown in FIG. 12. As a result, the bonding pads 4xe2x80x2 cannot be arranged in the corners of the semiconductor chip 2xe2x80x2, and accordingly it is difficult to decrease the pitch between the bonding pads 4xe2x80x2.
In addition to the above, in the above-mentioned xcexcBGA structure, since the lead 7xe2x80x2 to be connected to the bonding pad 4xe2x80x2 of the semiconductor chip 2xe2x80x2 in the TAB tape 5xe2x80x2 is supported in a cantilever state from an edge portion of the insulator tape 6xe2x80x2, the lead 7xe2x80x2 itself needs to have a strength to a certain degree, and if not, there is caused a problem of strength that the lead 7xe2x80x2 is easily deformed. Further, in a case where the surface of the lead 7xe2x80x2 is plated with gold so as to be easily connected with the bonding pad 4xe2x80x2, it is required to arrange an additional leading-out lead to be used for the gold plating which is connected to the lead 7xe2x80x2.
An object of the present invention is to provide a structure of the semiconductor device of a CSP structure in which the limitation by the bonding tool is small and the bonding pitch of the semiconductor chip can be reduced to 100 xcexcm or less, and the chip shrink technique of a technique for lowering the cost can be employed, and, in connection with this, compatibility among packages can be kept.
Another object of the present invention is to provide a semiconductor device TAB tape used for manufacturing the above-mentioned semiconductor device and a useful method of manufacturing the TAB tape.
A still other object of the present invention is to provide a useful method of manufacturing the above-mentioned semiconductor device using the above-mentioned TAB tape.
The objects of the present invention described above can be attained by providing a semiconductor device comprising a semiconductor chip; a TAB tape being used by being directly laminated onto a circuit formed surface of the semiconductor chip or by being laminated through a stress moderating elastomer onto the circuit formed surface of the semiconductor chip, the TAB tape having leads made of a metallic film formed on an insulator tape having flexibility; and an externally connecting member formed in an end of the lead of the TAB tape, wherein the TAB tape has holes in the insulator tape, each of the holes corresponding to a bonding pad formed on a circuit formed surface of the semiconductor chip at a position corresponding to a position of the bonding pad; the lead being formed so as to bridge across the hole; the lead formed across the hole being joined to the bonding pad of the semiconductor chip.
Therein, in regard to the holes corresponding to the bonding pads, there are two cases where a hole is formed corresponding to each of a plurality of bonding pads formed on the circuit formed surface of the semiconductor chip and where a plurality of bonding pads are grouped and a hole is formed corresponding to the group of bonding pads. The both cases are within the scope of the present invention.
Further, the object of the present invention described above can be attained by providing a TAB tape for a semiconductor device being used by being directly laminated onto a circuit formed surface of the semiconductor chip or by being laminated through a stress moderating elastomer onto the circuit formed surface of the semiconductor chip, the TAB tape having leads made of a metallic film formed on an insulator tape having flexibility, which comprises holes in the insulator tape, each of the holes corresponding to a bonding pad formed on a circuit formed surface of the semiconductor chip at a position corresponding to a position of the bonding pad, the lead being formed so as to bridge across the hole.
Furthermore, the objects of the present invention described above can be attained by providing a method of manufacturing a TAB tape for a semiconductor device being used by being directly laminated onto a circuit formed surface of the semiconductor chip or by being laminated through a stress moderating elastomer onto the circuit formed surface of the semiconductor chip, the TAB tape having leads made of a metallic film formed on an insulator tape having flexibility, the method comprising the steps of preparing a tape member having metallic films formed on both surfaces of an insulator tape having flexibility; etching the metallic film formed on one side of the tape member to partially expose the insulator tape at least at positions corresponding to bonding pads formed on the circuit formed surface of the semiconductor chip; laser processing the exposed portions of the insulator tape to form holes corresponding to the bonding pads in the insulator tape at the positions corresponding to the bonding pads; and etching the metallic film formed on the other side of the tape member to form the lead so as to bridge across the hole.
Furthermore, the objects of the present invention described above can be attained by providing a method of manufacturing a semiconductor device, the method comprising the steps of preparing a semiconductor chip and a TAB tape for a semiconductor device being used by being directly laminated onto a circuit formed surface of the semiconductor chip or by being laminated through a stress moderating elastomer onto the circuit formed surface of the semiconductor chip, the TAB tape having leads made of a metallic film formed on an insulator tape having flexibility, and having holes formed in the insulator tape, each of the holes corresponding to a bonding pad formed on a circuit formed surface of the semiconductor chip at a position corresponding to a position of the bonding pad, the lead being formed so as to bridge across the hole; positioning the bonding pads of the semiconductor chip to the holes of the TAB tape for the semiconductor device; and pushing and jointing the lead formed across the hole onto the bonding pad of the semiconductor chip.